PCIe GEN6 PHY IP Core
EIC Product Code:
Designed for next-generation PCIe systems, the PCIe GEN6 PHY IP supports data rates up to 64GT/s per lane with advanced PAM4 signaling. It ensures efficient data handling for demanding applications such as AI, ML, high-performance computing, and modern storage technologies. With scalable throughput and a focus on reliability, this PHY IP simplifies integration into high-speed, data-intensive use cases.
The product is suitable for implementation on industry-leading FPGAs such as AMD Versal Premium and Altera Agilex-7. It supports PAM-4 signaling through FPGA transceivers and utilizes PIPE 6.x (SERDES architecture) for easy integration with Logic Fruit or any third-party PCIe 6.x controller IP. The system also supports PRBS testing, including loopback modes, and is compliant with different power states as specified by the PCIe PHY specification. It offers support for a 100 MHz common reference clock between the RC and EP, and includes FPGA native features such as DRP access, eye scan, PRBS/test pattern generation, and checker. Furthermore, it supports PCIe-compliant patterns, including Gen6 compliance/modified compliance (PCIe Base 6.2 sections 4.2.14-15), 52UI jitter measurement (PCIe Base 6.2 section 4.2.16), high swing toggle (PCIe Base 6.2 section 4.2.17), Gen5 compliance/modified compliance (PCIe Base 5.0 sections 4.2.10-11), and Gen5 jitter measurement (PCIe Base 5.0).
- Supports PRBS (Pseudo Random Binary Sequence) testing including loopback modes
- Supports different power states as defined in PCIe PHY specification
- Supports 100MHz common reference clock between RC and EP
- Supports the PCIe Gen6 compliance/modified compliance (PCIe base 6.2 sections 4.2.14-15)
- Supports 52UI jitter measurement (PCIe base 6.2 section 4.2.16)
- Supports High swing toggle (PCIe base 6.2 section 4.2.17)
