PCIE GEN 6 IP Core

EIC Product Code:

The product supports PCIe 6.x with full backward compatibility for previous generations and is capable of operating in both RC (Root Complex) and EP (Endpoint) modes. It supports signaling rates of 64 GT/s, 32 GT/s, 16 GT/s, 8 GT/s, 5 GT/s, and 2.5 GT/s, along with link width configurations for x8, x4, x2, and x1. Additionally, it allows bypassing transaction layers to reduce logic for LTSSM testing and supports PCIe Loss, L1 power states, as well as the newly added Lop power states. The system includes a normal and selective replay/retry mechanism, with configurable TC (Traffic Class) to VC (Virtual Channel) queue mapping and virtual channel management. It also supports Hot Reset and Disabled LTSSM modes, handles payload sizes up to 4K, and allows multiple functions. The product is capable of managing errors, interrupts, and messages, and supports forced error insertions. Furthermore, it features automatic lane and polarity detection and is synthesizable for both AMD and Intel FPGAs. The IP is synthesized on a 250 MHz clock, supporting 2048 bits (256 bytes) at the transaction layer on this clock frequency.